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三星Exynos4412 Cortex-A9 1.5GHz 四核处理器 S5E4412

Samsung Exynos4212Overview

Exynos 4412 (S5E4412) is a 32-bit RISC cost-effective, low power, performance optimized and
Coretex-A9 Quad Core based micro-processor solution for smart phone applications. To provide
optimized hardware performance for the mobile telecommunication services and general
applications on smart phone, Exynos 4212 adopts 64-bit/128-bit internal bus architecture and
many powerful hardware accelerators for different tasks. These tasks, for example are, motion
video processing, Image Signal Processing, display control and scaling. Integrated Multi Format
Codec (MFC) supports encoding and decoding of MPEG-2/4, H.263, H.264 and decoding of VC1. This
hardware Encoder/Decoder supports real-time video conferencing and digital TV out.

The memory system has dedicated DRAM ports and Static Memory port. The dedicated DRAM ports
support LPDDR2 interface for high bandwidth. Static Memory Port supports NOR Flash and ROM type
external memory and components.

To reduce the total system cost and enhance the overall functionality, Exynos 4212 includes many
hardware peripherals, such as TFT 24-bit true color LCD controller, Camera Interface, MIPI DSI,
CSI-2, System Manager for power management, embedded GPS and GLONASS, MIPI slimbus interface,
MIPI HSI, four UARTs, 24-channel DMA, Timers, General I/O Ports, three I2S, S/PDIF, eight IIC-BUS
interface, three HS-SPI, USB Host 2.0, USB 2.0 Device operating at high speed (480Mbps), two USB
HSIC, four SD Host and high-speed Multimedia Card Interface, Chip to Chip interface, and four
PLLs for clock generation.

Package on Package (POP) option with MCP is available for small form factor applications.

Features of Exynos 4412

The features of Exynos 4412 (S5E4412) are:
 ARM Cortex-A9 based Quad CPU Subsystem with NEON
 32/32 KB I/D Cache, 1 MB L2 Cache
 Operating frequency up to 800 MHz at 0.9 V, 1 GHz at 1.0 V, and 1.5 GHz at TBD V
 128-bit/64-bit Multi-layer bus architecture
 Core-D domain for ARM Cortex-A9 Quadl, CoreSight, and external memory interface
 Operating frequency up to 200 MHz at 1.0 V
 Global D- domain mainly for multimedia components and external storage interfaces
 Operating frequency up to 100 MHz at 1.0 V
 Core-P, Global-P domain mainly for other system component, such as system peripherals, peripheral
DMAs, connectivity IPs and Audio interfaces.
 Operating frequency up to 100 MHz at 1.0 V
 Audio domain for low power audio play
 Advanced power management for mobile applications
 64 KB ROM for secure booting and 256 KB RAM for security function
 8-bit ITU 601/656 Camera Interface supports horizontal size up to 4224 pixels for scaled and 8192
pixels for un-scaled resolution
 Multi Format Codec provides encoding and decoding of MPEG-4/H.263/H.264 up to 1080p@30 fps and
decoding of MPEG-2/VC1/Xvid video up to 1080p@30fps
 Image Signal Processing subsystem
 JPEG encoder supports various format.
 3D Graphics Acceleration with scalable Multicore GPU.
 2D Graphics Acceleration support.
 1/2/4/ 8bpp Palletized or 8/16/24bpp Non-Palletized Color TFT recommend up to SXGA resolution
 HDMI interface support for NTSC and PAL mode with image enhancer
 MIPI-DSI and MIPI-CSI interface support
 One AC-97 audio codec interface and 3-channel PCM serial audio interface
 Three 24-bit I2S interface support
 One TX only S/PDIF interface support for digital audio
 Eight I2C interface support
 Three SPI support
 Four UART supports three Mbps ports for Bluetooth 2.0
 On-chip USB 2.0 Device supports high-speed (480 Mbps, on-chip transceiver)
 On-chip USB 2.0 Host support
 Two on-chip USB HSIC
 Four SD/ SDIO/ HS-MMC interface support
 32-channel DMA controller (16 channels for Memory-to-memory DMA, 16 channels for Peripheral DMA)
 Supports 14  8 key matrix
 Configurable GPIOs
 Real time clock, PLL, timer with PWM, and watch dog timer
 Multi-core timer support for accurate tick time in power down mode (except sleep mode)
 Memory Subsystem
 Asynchronous SRAM/ ROM/ NOR interface with x8 or x16 data bus
 NAND interface with x8 data bus
 LPDDR2 interface (800 Mbps/pin DDR)
 Embedded GPS/AGPS/GLONASS.

获取 Exynos4412 S5E4412 Datasheet, Layout Guide,Hardware Design Guide ,Schematics ……
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7 已链接

  1. The Galaxy S III S5E4412 Processor—A Hacker’s Overview | xda-developers says:

    [...] the web for publicly available data sheets, best information listing I could come up with came from 8gpad. I’d like to take a minute and talk about the S5E4412 [...]

  2. The Galaxy S III S5E4412 Processor—A Hacker’s Overview « Simni says:

    [...] the web for publicly available data sheets, best information listing I could come up with came from 8gpad. I’d like to take a minute and talk about the S5E4412 [...]

  3. The Galaxy S III S5E4412 Processor—A Hacker’s Overview — jailbreakjunkie.com says:

    [...] the web for publicly available data sheets, best information listing I could come up with came from 8gpad. I’d like to take a minute and talk about the S5E4412 [...]

  4. The Galaxy S III S5E4412 Processor—A Hacker’s Overview | Mobile Daily says:

    [...] the web for publicly available data sheets, best information listing I could come up with came from 8gpad. I’d like to take a minute and talk about the S5E4412 [...]

  5. The Galaxy S III S5E4412 Processor—A Hacker’s Overview says:

    [...] the web for publicly available data sheets, best information listing I could come up with came from 8gpad. I’d like to take a minute and talk about the S5E4412 [...]

  6. The Galaxy S III S5E4412 Processor—A Hacker’s Overview - The 6 Android Lab says:

    [...] the web for publicly available data sheets, best information listing I could come up with came from 8gpad. I’d like to take a minute and talk about the S5E4412 [...]

  7. Samsung Galaxy SIII - Processor Overview(Advanced) says:

    [...] Galaxy SIII carries a Exynos 4412 processor ARM Cortex-A9,also called S5E4412. As being said in 8gpad.com This is a 32-bit performance effecient, powerful processor which packs 4 cores along with it [...]

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